This invention relates in general to characterization methods for use with LDMOS devices. More particularly, the invention relates to methods for characterization of LDMOS devices at the die reference plane.
Recently introduced Laterally Diffused Metal Oxide Semiconductors (LDMOS) increase operating frequency of silicon power FETs. LDMOS semiconductors incorporate a P+ sinker to connect the source terminal to the chip""s backside. With this structure, chips can be directly attached to metal bases, both to improve grounding and to reduce thermal resistance. LDMOS technology makes it possible to produce RF power transistors having high gain, useable efficiency, low thermal resistance, and superior performance when applied in cellular communication systems. High quality LDMOS products known in the arts such as, for example, devices available from Ericsson Telefonaktiebolaget L.M. of Sweden, employ gold metalization and gold wire connections. The use of gold eliminates temperature and metal fatigue problems associated with the use of other metals in LDMOS products. The use of gold at the source terminal of the LDMOS chip creates a problem with attaching the device to metallic midsections known in the art for device property characterization.
Various performance measurements and physical properties can be determined by the characterization of semiconductor materials and semiconductor devices. Many characterization parameters can be measured, such as for example, power-input versus output, 1 dB compression point, impedance, gain versus frequency, efficiency, temperature effects, and power versus voltage. Other property and performance parameters can be measured depending on design criteria. A problem associated with device characterization is that it is difficult to characterize a device alone without including characterization of parasitic measurements of the test equipment as well.
The characterization of state-of-the-art LDMOS devices is beset with additional problems due to the use of gold on the base of the device. The gold base makes the interconnection between a device and the test equipment difficult. Mechanical fastenings and/or specialized soldering techniques can be used, but tend to introduce parasitic measurements into characterization efforts. Similarly, packaged LDMOS devices can be characterized, but problems then remain with attempting to distinguish between device and package characteristics. Another difficulty sometimes encountered is that a test configuration should not preclude subsequent use of the device.
Accordingly, a need exists for a better way of characterizing properties of semiconductor devices such as LDMOS.
Disclosed are methods for characterization of Laterally Diffused Metal Oxide Semiconductors (LDMOS). The methods characterize LDMOS devices at the die reference plane. An LDMOS device is epoxied to a midsection for connection to a test fixture for characterization. The combined physical parameters of the LDMOS device and test fixtureare determined. Next, the measurements obtained are adjusted for the physical parameters of the test fixture alone, isolating the physical parameters characterizing the LDMOS device at the die reference plane. The methods have an advantage in providing characterization of LDMOS devices at the die reference plane with more accuracy than previous methods.
In the preferred embodiment of the invention, the LDMOS device source terminal is epoxied to a midsection for testing, which provides a ground plane for the LDMOS device.
The invention disclosed provides many advantages by reducing the possibility of parasitic measurements. Epoxying the LDMOS device directly to the midsection eliminates some of the variability in the test fixture configuration commonly found in the arts.
Further technical advantages are obtained by wire-bonding the LDMOS device to the test fixture transmission lines, further reducing parasitic measurements.
The practice of the invention has additional advantages in simplifying the characterization of the performance of a LDMOS device at the die reference plane, thereby decreasing the time-to-market of device product development, and reducing costs.